Regviz

Silicon Labs /EFR32MG24A020F1536IM48 /RAC_NS /ANTDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ANTDIV

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/RAC_S/ANTDIV#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INTDIVLNAMIXEN0)INTDIVLNAMIXEN0 0 (INTDIVLNAMIXRFATTDCEN0)INTDIVLNAMIXRFATTDCEN0 0 (INTDIVLNAMIXRFPKDENRF0)INTDIVLNAMIXRFPKDENRF0 0 (INTDIVSYLODIVRLO02G4EN)INTDIVSYLODIVRLO02G4EN 0 (INTDIVLNAMIXEN1)INTDIVLNAMIXEN1 0 (INTDIVLNAMIXRFATTDCEN1)INTDIVLNAMIXRFATTDCEN1 0 (INTDIVLNAMIXRFPKDENRF1)INTDIVLNAMIXRFPKDENRF1 0 (INTDIVSYLODIVRLO12G4EN)INTDIVSYLODIVRLO12G4EN 0 (OFF)ANTDIVSTATUS

ANTDIVSTATUS=OFF

Description

No Description

Fields

INTDIVLNAMIXEN0

INTDIVLNAMIXEN0
INTDIVLNAMIXRFATTDCEN0

INTDIVLNAMIXRFATTDCEN0
INTDIVLNAMIXRFPKDENRF0

INTDIVLNAMIXRFPKDENRF0
INTDIVSYLODIVRLO02G4EN

INTDIVSYLODIVRLO02G4EN
INTDIVLNAMIXEN1

INTDIVLNAMIXEN1
INTDIVLNAMIXRFATTDCEN1

INTDIVLNAMIXRFATTDCEN1
INTDIVLNAMIXRFPKDENRF1

INTDIVLNAMIXRFPKDENRF1
INTDIVSYLODIVRLO12G4EN

INTDIVSYLODIVRLO12G4EN
ANTDIVSTATUS

ANTDIVSTATUS

0 (OFF): Both antenna disabled

1 (ANT1): Antenna 0 enabled

2 (ANT2): Antenna 1 enabled

3 (BOTH): Both Antenna enabled

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data